1. Field of the Invention
The present invention relates to the field of timing analysis of integrated circuit designs.
2. Description of the Related Art
One of the important signals in the design of a digital system, such as a computer system, is the clock. Ideally, the clock signal is a periodic step waveform with abrupt transitions between the low and high values. The clock signal orders the multitude of events occurring in digital circuits.
Ordering the events occurring in a digital circuit can be compared to the function of a traffic light which determines which cars are allowed to move at an intersection. The clock also makes sure that all operations are completed before the next operation starts, just as a traffic light should remain green long enough to allow a car or pedestrian to cross the road. A clock can be adjusted just as the timing of a traffic light can be adjusted. Adjusting the timing of a traffic light can ensure that two cars traveling on intersecting roads do not both arrive at a traffic signal at the same time and both have a green (or red) light. Similarly, adjusting the clock of a digital integrated circuit can ensure optimal throughput and prevent collisions in data being transmitted.
FIG. 1A represents an idealized clock as a periodic step waveform with abrupt transitions. As shown in FIG. 1A, the transitions from the low value to the high value appear instantaneously. The change in voltage from the low value to the high value is represented by a vertical line. However, there can be a delay associated with transferring electrical charges along a conductor due to finite resistance and capacitance. Therefore, FIG. 1B represents a more realistic clock waveform. Referring to FIG. 1B, the change from a low voltage value to the high value is not instantaneous. Thus, clock signal transitions have a finite slope, or xe2x80x9cslew.xe2x80x9d
Referring to FIG. 1C, a register module can sample the value of the input signal at the rising edge of the clock. The value is preserved and appears at the output until the next cycle of the clock signal when a new sample is taken. FIG. 2A through FIG. 2C compare clock signals and the associated function of a hypothetical xe2x80x9cedge-sensitivexe2x80x9d register module.
For illustrative purposes, assume that an additional load has been connected to the circuit (such as additional registers) and the clock signal has deteriorated. Deterioration of the clock signal due to an additional load causes the slope of the line connecting the low voltage value and the high voltage value to become less steep. This slew degradation of the clock signal caused by the additional load can be seen by comparing clock signals xcfx86 and xcfx86xe2x80x2 in FIG. 2A. An idealized function of a register output is shown in FIG. 2B. When the deterioration is within acceptable limits, the behavior of the register is not significantly affected and the expected output is maintained for the duration of the clock cycle. However, when the deterioration of the clock slew exceeds an acceptable value, the register can produce unexpected results. For example, when clock slew degradation is severe, the register output may make an incorrect transition, such as the one shown in FIG. 2C.
Thus, global effects, such as adding registers or other load to a clock network, can change the behavior of an individual module of an integrated circuit. The effects are not the same for all modules, but are dependent upon the particular register circuit. Propagation of these erroneous output signals can cause system malfunctions and unexpected shutdowns.
Effects of clock signal deterioration manifested as clock skew in operations of synchronous digital circuits are shown in FIGS. 3A through 3C. FIG. 3A shows a circuit including two cascaded registers. Both registers shown in FIG. 3A are xe2x80x9cedge-sensitivexe2x80x9d and operate on the rising edge of the clock signal. Under normal operating conditions, the input is sampled by the first register. The sample taken by the first register appears at the output, labeled Out in FIG. 3A, one clock period (or one cycle) later.
The clocks can become misaligned due to uncertainties associated with wire delay, clock driver size and variations in process, voltage and temperature across the integrated circuit chip. As a result, the registers may interpret time indicated by the local clock signals (xcfx86 and xcfx86xe2x80x2 in FIG. 3A) differently. Consider the case when the clock signal for the second register is delayed, or xe2x80x9cskewed,xe2x80x9d as shown in FIG. 3B. The late arriving rising edge of the delayed clock xcfx86xe2x80x2 postpones the sampling of the input of the second register.
FIG. 3B shows a signal labeled In, shown as a dashed line, which represents the input to the first register when the clock xcfx86 rises. At time T1, the input has a high value. However, the input as provided to the second register at time T2, the second rising edge of the clock signal xcfx86xe2x80x2(skewed) after one cycle, may have an erroneous low value when provided to the second register if skew exists between clocks xcfx86 and xcfx86xe2x80x2.
If the time to propagate the output of the first register to the input of the second register is smaller than the clock skew, the value of the input at time T1 may be overwritten prior to time T2 at the second register. Overwriting the value is due to the falling input at the first register which is sampled on the earlier rising edge of clock xcfx86 and propagated to the second register prior to T2. Consequently, the second register already contains the low value at time T2, when the input for register 2 is sampled. This causes the output to change prematurely, as shown in FIG. 3C, which shows the correct output Out and the erroneous output Outxe2x80x2. The signal Outxe2x80x2 has a low value at the rising edge T2 of the clock instead of a high value.
Differences in clock arrival times are an increasing concern for high-speed circuit designers. Cycle times have been dramatically decreasing, driven by faster transistors and by more aggressive designs that use fewer gates per cycle. Differences in clock arrival times are increased by variables such as process variations, environmental variations, wire delay and clock loading. With decreasing clock cycle times, clock skew is consuming an increasing fraction of the cycle time and less time is available to perform logic operations. Therefore, designers have been forced to pay increasing attention to clock skew.
Conventional tools for static timing analysis, including commercially available static timing analysis tools, allow for a delay to be introduced for each clock and a single uncertainty skew value that applies to all domains of the circuit. However, uncertainty can be introduced by a number of variables, each having a different skew value, as described above. In such cases, static timing analysis with a single uncertainty skew value is insufficient. Furthermore, a given integrated circuit may include a large number of xe2x80x9cdomainsxe2x80x9d that are affected differently by clock skew. A designer may wish to eliminate clock skew in a critical path for the circuit, and/or to design the circuit and clock network to include less clock skew between nearby modules than between modules farther apart. What is needed is a more accurate means to consider clock skew in the design of high-performance digital systems.
In accordance with the present invention, a method for considering clock skew in designing digital systems is provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew. The method models skew by taking into account both systematic variation in clock arrival time and xe2x80x9cjitter,xe2x80x9d which includes the temporal variation in clock arrival time due to variables such as process, temperature and voltage fluctuations. The method can be implemented using a software application. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.
In one embodiment, a method includes selecting a domain from multiple domains representing an integrated circuit, wherein each domain has a respective clock delay. The method further includes determining a respective skew delay relative to the selected domain for each domain. The method also includes adding the respective skew delay to the respective clock delay to form a respective sum relative to the selected domain for each domain. The respective sums model clock skew relative to the selected domain. The method is repeated for each domain.
The method can include determining whether a path originating in an originating domain of the domains and terminating in the selected domain has a timing violation using the respective sum for the originating domain relative to the selected domain. The respective skew delay relative to the selected domain for each domain corresponds to one of several clock skew values that can be determined by an administrator; for example, the administrator may choose to model local, regional and global skew or any number of skew value groupings.
In one embodiment, determining the respective skew delay for each domain relative to the selected domain involves selecting the respective skew delay from a clock skew matrix. The selected domain and the given domain indicate the row and column from which the respective skew delay is to be selected.
One embodiment includes determining top paths for each selected domain. Top paths are determined by calculating a respective slack value for each path terminating in the selected domain, selecting largest timing violations from the respective slack values for each path. Each path having one of the plurality of largest timing violations is a top path.
The invention also includes a system, computer program product, and computer system designed to implement the methods described above.
The disclosure contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the disclosure is illustrative only and is not intended in any way to be limiting.